1. Field of the Invention
The present invention relates to a digital filter for filtering data to which oversampling is carried out, and a data processing method thereof.
2. Description of Related Art
As a digital filter, for example, an FIR (Finite Impulse Response) filter whose impulse response lasts for finite time, is known. The output of the FIR filter, that is, the filter characteristic, is obtained by weighting each output of the multistage registers in the FIR filter with a predetermined weighting coefficient, and by adding all of the weighted values. In order to obtain the desired filter characteristic, the weighting coefficient by which each output of the registers is multiplied is made to correspond to the impulse response of the desired filter characteristic. Further, oversampling may be carried out in order to decrease unnecessary signals caused by folding.
For example, FIG. 3 is a view showing a circuit configuration of an FIR filter 200 when fourfold oversampling and filtering are carried out to input data with data length of N. Further, the clock signal in FIG. 3 is a signal for taking synchronism of action of each circuit in the FIR filter 200.
At first, zero value interpolation to data length of 4N is carried out to the input data with data length of N in an interpolation circuit 210. Concretely, as shown in FIG. 4, interpolation is carried out to the input data by inserting three “0”s between each adjacent data in the input data with data length of N, in other words, three “0”s are inserted after each original data in the input data, so that data with data length of 4N is generated. Then, the data with data length of 4N is inputted into the FIR filter 200.
As shown in FIG. 3, the FIR filter 200 comprises 4N-stages of delay circuits 60-n (n=1,2,3, . . . , 4N), multiplication circuits 70-n which are the same number (4N) as the delay circuits 60-n, and an adding circuit 80.
The delay circuits 60-n shift the inputted data for every timing of the clock signal which is inputted, and output the shifted data to the latter stage delay circuits 60-n. For example, the delay circuit 60-1 outputs the shifted data to the delay circuit 60-2, or the like. Further, the shifted data are outputted to the multiplication circuits 70-n at the same time, in parallel. The multiplication circuits 70-n multiplies the data inputted from the delay circuits 60-n by the predetermined coefficients h(n), respectively. Then, the multiplication circuits 70-n output the multiplied results to the adding circuit 80.
Further, the adding circuit 80 adds all of the multiplied results inputted from the multiplication circuits 70-n, and outputs the added result. The added result from the adding circuit 80 becomes the output data (filter characteristic) of the FIR filter 200.
That is, the data to which zero value interpolation is carried out, and which is inputted into the FIR filter 200 are shifted for every timing of the clock signal, and each shifted data is multiplied by the predetermined coefficient h(n). Then, the multiplied results are all added, so that the desired filter characteristic can be obtained.
FIGS. 4A and 4B show the relation between the input data and the output data (filter characteristic) outputted from the FIR filter 200. As shown in FIG. 4A, zero value interpolation to data length of 4N is carried out to the input data with data length of N by inserting three “0”s between each adjacent data of the input data with data length of N (that is, three “0”s are inserted after each original data), in the interpolation circuit 210, and the data with data length of 4N is inputted into the FIR filter 200. Then, each data in the data to which interpolation to data length of 4N is carried out is multiplied by the predetermined coefficient h(n) in the multiplication circuits 70-n. 
For example, as shown in FIG. 4A, the data D(N) is multiplied by the coefficient h(1), the three “0”s inserted between the data D(N) and data D(N−1) are multiplied by the coefficients h(2), h(3) and h(4), respectively, the data D(N−1) is multiplied by the coefficient h(5), or the like.
All of the multiplied results are added in the adding circuit 80, and the added result is outputted from the FIR filter 200. That is, the output data from the FIR filter 200 is (data D(N)×coefficient h(1))+0+0+0+(data D(N−1)×coefficient h(5))+. . . +(data D(1)×coefficient h(4N−3))+0+0+0, and this value becomes the desired filter characteristic in this case.
Further, FIG. 4B shows the relation between the input data and output data of one clock later than the case shown in FIG. 4A. As shown in FIG. 4B, each data in the input data to which zero value interpolation is carried out is shifted for one clock by the delay circuits 60-n. Thereafter, in the same way as in FIG. 4A, the shifted data are multiplied by the predetermined coefficients h(n), respectively, in the multiplication circuits 70-n. 
For example, as shown in FIG. 4B, the data D(N) is multiplied by the coefficient h(2), the three “0”s inserted between the data D(N) and data D(N−1) are multiplied by the coefficients h(3), h(4) and h(5), respectively, the data D(N−1) is multiplied by the coefficient h(6), or the like.
All of the multiplied results are added in the adding circuit 80, and the added result is outputted from the FIR filter 200. That is, the output data from the FIR filter 200 of one clock later is (data D(N)×coefficient h(2))+0+0+0+(data D(N−1)×coefficient h(6))+. . . +(data D(1)×coefficient h(4N−2))+0+0+0, and this value becomes the desired filter characteristic in this case.
However, when oversampling is carried out to input data, the more the magnification of oversampling increases, the more the number of multiplication circuits required for convolution operation of an FIR filter increases. For example, when fourfold oversampling is carried out, the number of four times as many multiplication circuits as the case not carrying out oversampling is required.
In this case, as shown in FIGS. 4A and 4B, since the multiplied results of the portions of the data to which interpolation is carried out by inserting “0”s are “0”s after all, unnecessary operation is performed. Further, there is a problem that the circuit scale of the FIR filter is increased because of the increase of the number of required multiplication circuits used in the circuit.